Computer systems and other electronic devices typically include a main memory that is used to provide relatively fast access to information such as instructions and data. One form of such a memory is a dynamic random access memory (DRAM). DRAM includes memory cells that are arranged in an array of rows and columns. Each memory cell can store a single bit of information. DRAM is a volatile memory which means that the memory cells only store the information as long as power is provided and as long as the memory cells are refreshed on a periodic basis. If the power is turned off or the memory cells are not refreshed, information stored in a DRAM is lost.
During normal operation, an auto refresh operation is performed periodically to refresh the memory cells in a DRAM. An auto refresh operation is performed in response to an auto refresh command that is issued by a memory controller connected to the DRAM. Unfortunately, information in the DRAM cannot be accessed by the memory controller during an auto refresh operation. As a result, the memory controller cannot perform memory operations, such as reads and writes, to the DRAM until an auto refresh operation completes. The delay in performing these memory operations may cause the performance of the computer system or other electronic device to suffer.
As the size and density of memory cells in a DRAM increase, the time it takes to perform an auto refresh operation typically increases as well. The time increase occurs because of the increase in the number of memory cells that need to be refreshed. The time increase also occurs because of internal electrical limitations such the sensing noise that increases as the number of rows of memory cells being refreshed at any given time increases.
It would be desirable to reduce the amount of time that a memory controller cannot access information in a DRAM. Accordingly, it would be desirable to improve the auto refresh operation in DRAMs.